Superheroes of SoC | Solutions & Resources for Mixed-Signal SoC Design.

Recent Blogs

June Conferences: DAC and Symposium on VLSI Technology and Circuits

By Brian Bailey on April 24, 2012

176 comments

Before we know it, it will be summer and that means conferences.

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Power integrity -- How much does it matter?

By Brian Bailey on April 17, 2012

141 comments

If you have been following my month of power over on the EE Times EDA Designline, you will know that I have been featuring books that tackle the subject of power integrity.

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Time to rethink EDA flows and tool infrastructure

By Brian Bailey on April 5, 2012

156 comments

Recently, I have had the pleasure of talking to a number of entrepreneurs within the EDA space and got to hear some of their concerns and recommendations for people thinking about starting a new company.

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News Spotlight

Netronome reduces SoC power use with timing tricks

May 14, 2012

Cadence Design Systems claims that Netronome designers achieved a 29 percent reduction in power consumption using Cadence's latest Encounter 11.1 technology thereby providing performance advantage on its low-power "green" SoCs targeting the secure virtual cloud and data center markets.

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Startup claims 'Holy Grail' of SoC design

April 23, 2012

The first automated software-to-chip dream came out of the closet Monday (April 23), when Algotochip Corp. (Sunnyvale, Calif.) claimed to be able to produce a system-on-chip (SoC) design from a C-code specification in just eight to 16 weeks.

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Design for power methodology

April 20, 2012

Power is a daunting challenge for modern system-on-chip (SoC) designs, from both the power consumption and power integrity perspectives.

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Featured Resources

DATA SHEET: Talus Vortex FX

Talus Vortex FX, with Magma’s new Distributed Smart Sync™ technology, delivers unmatched throughput for physical design implementation. The Distributed Smart Sync technology intelligently manages the process of distribution and synchronization throughout each of the design steps in the Talus Vortex physical implementation flow.

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WHITEPAPER: Tekton – Next-Generation Static Timing Analysis Platform

This white paper describes how Tekton addresses the dramatic increase in the number of static timing analysis (STA) scenarios, the lengthy engineering change order (ECO) process and the need for increased accuracy for analysis of the final violations.

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WEBCAST: Solving Design Challenges Visually with the Talus Visual Volcano

In IC design, the faster you can identify problems or determine which approach is best, the faster you can reach your design goals. In this quick webinar, you’ll learn how you can accelerate design debugging and improve communication between team members with the Talus Visual Volcano.

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Featured Video

Titan: Fastest Path to Mixed Signal Silicon
Mar Hershenson provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.

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Talus Design RTL Synthesis - Talus Design is a comprehensive RTL synthesis solution that includes production-proven RTL synthesis, physical synthesis and a timing analyzer.

Webcast Highlights

SoC Designers, Get a Clear Vision of 20-nm Success

With lithography limits, double patterning, high-k gates, low-k interconnects and myriad new requirements, the path to silicon success at the 20-nm node can look a little fuzzy. You need an advanced, scalable, integrated SoC design environment that delivers fast and predictable timing and layout closure. Attend this webcast to get a clear vision of how Magma's Silicon One technology can get your 20-nm SoC to silicon fast and with better results.