Peggy Aycinena

Peggy Aycinena is a Freelance Journalist, Editor of EDA Confidential, partner in EDAMarket, and a contributing editor to the DAC.com Knowledge Center.

Aycinena served as a Contributing Editor to EDA Weekly, Managing Editor of Visual Studio Magazine, Copy Editor of Chip Design Magazine, and Editor of ISD Magazine. Her articles have appeared in IEEE Design & Test, CACM, ISD Magazine, EETimes, Intelligent Enterprise, on ISD.com, EETimes.com, EEDesign.com, TechOnline.com, EDAToolsCafe.com, EDAVision.com, ChipDesignMag.com/edanation, SOCcentral.com, and ftponline.com, as well as the occassional blog on EDADesigdnLine.com and EDACafe.com. Aycinena has degrees in biophysics and electrical engineering from UCB and SFSU, respectively, and studied control systems at Stanford while working at NASA. She drinks coffee, plays the accordion badly, and is often accused of talking too fast.

Featured Video

Titan: Fastest Path to Mixed Signal Silicon
Mar Hershenson provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.

· watch more SoC videos

Talus Design RTL Synthesis - Talus Design is a comprehensive RTL synthesis solution that includes production-proven RTL synthesis, physical synthesis and a timing analyzer.

Webcast Highlights

SoC Designers, Get a Clear Vision of 20-nm Success

With lithography limits, double patterning, high-k gates, low-k interconnects and myriad new requirements, the path to silicon success at the 20-nm node can look a little fuzzy. You need an advanced, scalable, integrated SoC design environment that delivers fast and predictable timing and layout closure. Attend this webcast to get a clear vision of how Magma's Silicon One technology can get your 20-nm SoC to silicon fast and with better results.