At DAC 2010 in Anaheim, many people insisted that 3D-IC technology would be the hot topic next year. Believe that at your own peril, however, because the topic's already here. Over the last 4 weeks in Northern California alone, there have been hours and hours of tech conference air time dedicated to 3D-IC issues, including at the IEEE Nanotech Council Half-Day Seminar on November 16th in Santa Clara, at IEDM 2010 on December 6-8 in San Francisco, and at TechVenture's 3D Archtecures on December 9-10 in Burlingame.

One major take away from listening in: 3D ICs are in production, and the issues surrounding their design and manufacturing are being resolved at a break-neck pace. If you wait until DAC 2011 in San Diego to come up to speed on 3D, you'll be too late.

At the IEDM Press Luncheon on December 6th, Executive Committee member John Suehle noted that TSVs [thru-silicon vias] were being discussed in sessions on reliability, hence these structures are already in production and are no longer a novel or emerging technology.

That's not to say that all of the challenges have been resolved, of course, but a number of companies have been producing working 3D devices for some time. Tezzaron is one of those companies; CEO Bob Patti, during his 30-minute presentation at the TechVenture event on December 9th, held up a gleaming 300-mm wafer and announced this Tezzaron wtw [wafer to wafer] product, already several years old, contained upwards of a million TSVs. Patti also gave high praise to Magma Design Automation for their crucial assist with Tezzaron's design efforts, Magma tools allowing Tezzaron to deal with the boatloads of data needed to execute on their complex designs.

Also in Burlingame on December 9th, TechSearch International President Jan Vardaman detailed the October 26th announcement from Xilinx describing the company's “Stacked Silicon Interconnect” device – multiple FPGAs successfully layered into a single package, thanks to the magic of TSVs, micro bumps, and a generous dollop of Silicon interposer.

Vardaman also noted that, although “real engineering work in 3D is underway”, huge issues remain: resolving thermal and mechanical stresses between stacked layers of silicon, access to adequate EDA tools [Bob Patti's comments on Magma, notwithstanding], challenges related to testing 3D devices, and obtaining sufficient reliability data from the foundries.

Meanwhile, Synopsys' SVP Antun Domic – also speaking at the TechVenture 3D event on December 9th – presented a high-level overview of 3D integration challenges, and noted that his company is collaborating with partners “to make sure all of the EDA ingredients [required for 3D integration] will be available in a timely manner.”

What constitutes a “timely manner” has yet to be proven, but if you want to guarantee your own future in the industry – either as a chip designer, or as somebody who creates the tools that facilitate the work of that designer – you better be serious about playing the game, The Game of 3D. It only has 3 rules ...

Design. Deploy. Dominate.