Buried cost concerns haunt the 3D IC
By Chris Edwards | June 13, 2011
Interest is building around the idea of the 3D integrated circuit (IC). It can potentially squeeze entire sensors into one tiny plastic package and deliver tiny computers with massive amounts of high-speed memory. But, in a sense, the industry has been here before. Back in the early 1990s, multichip modules as they were known before they got the 3D rebranding were seen as a to deal with the growing problems of designing dense integrated circuits (ICs).
Unfortunately, the technology was expensive to implement, relegating to specialised applications except for the situation where Intel, in order to keep up with its performance targets for PCs, adopted them for some of its Pentium processors.
Manufacturers also found that, outside of some specialised RF applications where it made sense to put components directly onto a ceramic substrate, memory was the only thing you could expect to put in a multichip module and expect it to work. The industry developed screening procedures to make it easier to weed out duds before they were integrated into a module where they could be fully tested. Realistically, only memory was predictable enough to be supplied in the form of known good die.
Where possible, Intel and others always stepped back to monolithic silicon. The arrival of the mobile phone changed the situation for 3D ICs as advances in wirebonding, wafer thinning and handling made it cost effective to combine different forms of memory in one package and save board space.
The increasing cost of developing SoCs is making companies outside the memory business look seriously at 3D ICs to stack other ICs than memory – and use much closer coupling between the individual chips to provide a performance boost. At first sight, it looks to be a good thing for mixed-signal design.
You can kiss goodbye to substrate-borne interference from noisy digital circuits – mostly. You can breathe a sigh of relief from not having to deal with immature process models and limited voltage headroom. And say hello to mature, well-understood processes and, if you need them bags of readymade circuit-level IP. Not only that the wafer cost for the mixed-signal parts can be much lower than that of an advanced process needed for dense digital circuitry.
But the move to 3D is not a one-way bet. Cost remains a significant issue. Even the most optimistic projections for the additional processing cost of putting dice on top of each other using high-speed, low-inductance interconnect is around 15 per cent per die. This could easily wipe out the wafer cost advantage of using cheaper, older processes for mixed-signal sections.
There are also practical issues that will tend to increase overall cost. The issue is less serious for 3D ICs that use a common silicon interposer as techniques similar to flip-chip bonding can be used to take conventional dice and mount them in one package with high-performance interconnect. However, you do have to factor in the cost of the silicon interposer itself, which, to maintain high interconnect density may need a reasonably advanced base process for the metallisation. For example, Xilinx uses a 65nm process for the interposer in its multichip FPGAs.
Faced with this, the through-silicon via (TSV) looks ideal as you can dispense with the largely passive silicon IC underneath and you get to save more board space by stacking devices vertically.
Ideally, you would have the contact on the lowest layer next to the transistors that talk to it – assuming it's not just a through-die connection. Unfortunately, this is hard to make and causes high stresses around devices that don't work well with those kinds of stresses. So, the contacts have to go in at least halfway up the metal stack where the lines are comparatively wide. So, not only do the vias wipe out precious die area, they block the routing as well, which can cause problems for shape-sensitive analogue routing.
Even with via-middle and via-last processes, there are still significant stresses around the large copper-filled via: the silicon is 'pulled' toward the via. This is a problem for digital but it's more serious for analogue circuitry. So the keep out zone around the TSV can be pretty big for active devices. Simulations by IMEC and Synopsys have indicated that it this zone is ten times larger for analogue devices than digital. The simulation work showed that the stress around a single TSV calls for a keep-out zone of around 20µm.
It makes sense to put clusters of TSVs close to each other and simply treat them as an unusable block. But the keepout zone can expand to 150µm or 200µm. This will necessarily limit the density of TSV contacts, perhaps forcing the mixed-signal devices to the top of the stack to limit the number of through connections that affect the die. And it will increase the die size of the mixed-signal part, which might be tolerable in terms of cost given the lower wafer price but still needs to be factored in.
3D certainly looks interesting for mixed-signal SoCs, but the higher cost of designing for monolithic silicon could pay off in better margins for the final product.
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