DVCon: Truth & Consequences
By Peggy Aycinena | March 2, 2011
There's always breaking news at conferences and DVCon 2011 is no exception, with UVM 1.0 and the Synopsys-Xilinx FPGA prototyping manual among this year's announcements. Sometimes it's useful to track the deeper truths, however, and received wisdoms upon which the sessions and news reside.
Here's a Baker's Dozen worth of soundbites, mostly off-the-record, jotted down during various conversations with DVCon attendees in and around sessions this week in San Jose.
One – It's always Us versus Them at conferences: SoC design v. IP development/integration. Digital v. Analog. Software v. Hardware. Reality v. Market-speak. Real-world engineering v. The Vision.
Two – EDA vendors should remember that when they change something it means the engineers who use their tools now don't know how to use the tool as well. Then, when the engineers have got problems, they have to go back to an earlier version of the tool to check on that 20% of the design that's not working out. Sometimes they even have to start all over again completely from scratch.
Three – Analog engineers just aren't like you and me, unless you're among those several thousand people worldwide who really do analog design. They want to stay locked up in their offices and don't want to talk to anybody, least of all the digital guys. Today in the world of AMS design, however, the analog guys are being pried out of their offices to learn about the culture, language, and mindset of their digital teammates – and the requirements of verification.
Four – Analog designers do not believe that tools can do much for them, if anything at all. They don't know how automation can help them be better at their art, because there's never a perfectly optimized answer for what they're trying to achieve. There's only better, and slightly better.
Five – FPGAs are becoming both big and badass. They can do all sorts of stuff that their far-more-expensive friends in the ASIC world can't do, because nobody can afford to produce the ASICs that the FPGAs are standing in for.
Six – An eternal question that will never be answered: Are people drawn to engineering because of their particular psychological profile, or do they assume that profile in the process of becoming engineers? What's that profile? No-frills thinking, nuts-and-bolts attitudes, reality trumps BS.
Seven – A testbench is comprised of libraries of components. Hence, it's reusable within reasonable limits.
Eight – Verification is not the problem, even though people who are verification specialists think that it is. For people who run design projects, however, verification is just part of the process. It's just one of the 10 or 20 problems they face, including software planning, architecture, marketing, and manufacturing. I hate to burst anybody's bubble, but nobody really gives a ratsass about verification standards, testbenches, or any of the rest of it.
Nine – Software content is king these days in digital product development. Don't forget Gary Smith's battle cry: “It's the software, Stupid!”
Ten – UVM is a great step forward for the industry, because at the end of the day UVM is about a standard that will help real people do their work. There were over 200 people at the UVM tutorial on Monday, which shows just how much interest there is in the industry for this standard.
Eleven – Verilog AMS is essentially merging with SystemVerilog AMS, because it's all about the pain point of integrating mixed-signal with analog design.
Twelve – SystemC and SystemVerilog get along just fine. They co-exist because they start at different points in the design, plus their customer bases are completely different. If you're expanding up from Verilog, you go to SystemVerilog. But if you're trying to go down from a model, an ESL model, you want to go to SystemC.
Thirteen – IEEE rules continue to disallow recruiting at IEEE-sponsored conferences. But Accellera has never had those kinds of prohibitions, which is why Qualcomm got to host their reception and recruiting event at DVCon. Nonetheless, going forward companies might object to having their employees attend conferences where recruiting's going on. The truth is, however, recruiting's always taking place at conferences, even at IEEE-sponsored events. It's just never talked about openly.
Fourteen – Per Wally Rhines' Tuesday afternoon keynote: The verification engineer is no longer a 2nd-class citizen. In fact, the time has possibly come that the designer will actually be subordinated to the verification guy.
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