Power integrity -- How much does it matter?
If you have been following my month of power over on the EE Times EDA Designline, you will know that I have been featuring books that tackle the subject of power integrity. It should tell you something that I am featuring four of them — all very different books.
This is perhaps a significant indication of the importance and complexity of this subject. Madhavan Swaminantha and A Ege Engin point out in their book “Power Integrity Modeling and Design for Semiconductor Systems“: managing power integrity is the process by which the variation on the power supply of the transistors can be maintained within a specified tolerance value. Noise on the power supply can have a direct influence on the speed of an integrated circuit, and hence supplying clean power is a very important element in the design of a computer system.
Raj Nair and Donald Bennett point out in their book “Power Integrity and Management for Integrated Circuits“: we must question the nature of power connections into a chip, internal power distribution, and the architecture of chip power grids. ICs now handle multiple clock and voltage domains, and are beginning to resemble system boards of the recent past, raising questions about capacitance and the power grid’s partitioning and electrical characteristics.
Pandit et al concentrate on I/O interfaces in their book “Power Integrity for I/O Interfaces.” They say an Input/Output (I/O) interface, when in operation, produces current in power and ground nodes. This current produces the noise, which is the source for the power integrity effects. The rate of change of current and the effective loop inductance of the Power Distribution Network (PDN) determine the noise. Clearly power integrity, signal integrity, and performance directly impact each other.
Eric Bogatin’s book “Signal and Power Integrity — Simplified” has been updated with a major new chapter on the design of PDNs. While this book concentrates more on the board and packing effects of the PDN it is an important upgrade to a well-respected book on signal integrity.
With an increasing number of chips requiring multiple power and voltage domains, and blocks utilizing variable voltage, it is becoming necessary to bring the voltage regulators on chip — something that has long been considered a board component. Integrating them on chip enables much faster response times and minimizes some of the negative aspects of dealing with the package and board level effects. However, powering up part of the design can cause large inrush currents that can then perturb other parts of the design. Also these large currents can cause problems with electromigration.
It has thus become essential that the entire power delivery system is designed at the system-level and carried through all stages of the design of the chip and board design. This is also placing some new demands on existing tools, such as logic simulators that have no concept of variability in voltage. This in turn can affect performance in complex ways.
So, the bad news is that chip-level power delivery networks are a complex and growing problem, but the good news, as often happens, is that much of the necessary ground work has already been covered by the board community and a lot of it is adaptable to this new environment.
What do you think? Post your comment below.
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