Tough Trends in SOCs
Like every field of engineering and computer science, SOC design has its own unique Grand Challenges related to the latest trends in the technology. In a recent conversation with Dr. Pranav Ashar, CTO at Real Intent, we talked about what those trends might be.
Ashar said, “The trends today in SOCs have three components – raw complexity, aggressive architecture, and timing constraint management. The first is due to the sheer scale of the chips – up to 100 million gates without individual models, which is why this raw complexity is pushing the limits of the EDA tools.
“With regards to the second trend: For various reasons SOCs are also challenging current ideas in circuit architecture, and blurring the boundary between functionality and timing. Many chips have islands of [computation], and although each of these islands is individually synchronous, that is not the case globally. They're locally synchronous, but globally asynchronous. Today you may [encounter up to] a thousand clocks across a chip, and clearly you can't send data to all parts of that chip, so you absolutely have to do islands.
“At that same space, SOCs are true systems, not just logic, and have to [interface] with the real world, plus have a lot of dynamic control for power, clock gating, and DFT structures on the chip. And, each component works at its own chosen frequency – some at really high speeds, and some merely at kilohertz – making all of this design work a real nightmare.
“For the third trend: Again because SOCs are true systems, the timing [constraints needed] to get closure are not simple any more. Looking at the volume and complexity of these constraints, plus managing all parts of the chip – it's a productivity nightmare.
“Of course, all three of these trends are made even more difficult, because we've still got some generations of shrinks to go, plus we also have [to master] all of 3D. The results are such that even more transistors will be available over the next 10 years in a single package. How to harness all of this in a useful manner is still not well understood.
“We will need newer architectures to harness all of these transistors, and to handle the power dissipation and interactions with memory. Also, we can't keep increasing the clock frequencies, so the only way to [deal with that] is with parallelism in the architecture, but how do we do the programming?
“Finally, there's verification. When you have a chip with 100 million gates, and you're doing a comprehensive analysis, the goal is to improve the productivity of the verification engineer. That includes not wanting to burden the guy with a big report, but delivering precise information that gives the end user a critical list of actionable items.”
Not surprisingly, Dr. Ashar is confident that Real Intent is meeting the verification and reporting needs of their customers effectively and intelligently today. He closed, “The four horses of the Apocalypse in verification are speed, capacity, comprehensiveness, and usability. These are the metrics for judging a verification tool, and we believe our solutions meet them all.”
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An interesting piece of work by Peggy. I loved to read this short article and discussion with Dr.Pranav of Real Intent. He tried to well explain the three components of the present trend. From his plans, it looks very difficult to apply these trends. Is there any link to them to which I can take some prints with clp 300 toner. He explained it very easily but it is going to be a very tough task for them to make it a practical one. He has long plans about the coming ten long years.
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